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| IN74LVU04 HEX INVERTER The 74LVU04 is a low-voltage, Si-gate CMOS device and is pin compatible with the 74HCU04. The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage with unbuffered outputs. * * * * Wide Operating Voltage: 1.0/5.5 V Optimized for Low Voltage applications: 1.0/3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current 14 1 14 1 D SUFFIX SOIC N SUFFIX PLASTIC ORDERING INFORMATION IN74LVU04N Plastic IN74LVU04D SOIC IZ74LVU04 Chip TA = -40 / 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND FUNCTION TABLE Input Output A Y L H H L 1 IN74LVU04 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC supply voltage (Referenced to GND) V -0.5 / +7.0 1 IIK * DC input diode current mA 20 IOK *2 DC output diode current mA 50 IO *3 DC output source or sink current mA 25 -bus driver outputs ICC DC VCC current for types with mA 50 - bus driver outputs IGND DC GND current for types with mA 50 - bus driver outputs 750 mW PD Power dissipation per package, plastic 500 DIP+ SOIC package+ Tstg Storage temperature -65 / +150 C 260 TL Lead temperature, 1.5 mm from Case for C 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to 1.0 5.5 V GND) VIN, VOUT DC Input Voltage, Output Voltage 0 VCC V (Referenced to GND) TA Operating Temperature, All Package -40 +125 C Types ns 500 t r, tf Input Rise and Fall 1.0 VVCC <2.0 V 0 200 Time 0 2.0 VVCC <2.7 V 100 0 2.7 VVCC <3.6 V 50 0 3.6 VVCC 5.5 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. * 2 IN74LVU04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Test VCC, 25C -40C / 85C -40C / Symbol Parameter Conditions V 125C min max min max min max 1.0 1.0 1.0 VIH High-Level 1.2 1.6 1.6 1.6 Input Voltage 2.0 2.4 2.4 2.4 2.7 2.4 2.4 2.4 3.0 2.4 2.4 2.4 3.6 3.6 3.6 3.6 4.5 4.4 4.4 4.4 5.5 0.2 0.2 0.2 VIL Low -Level 1.2 0.4 0.4 0.4 Input Voltage 2.0 0.5 0.5 0.5 2.7 0.5 0.5 0.5 3.0 0.5 0.5 0.5 3.6 0.9 0.9 0.9 4.5 1.1 1.1 1.1 5.5 1.0 1.0 VOH High-Level VI = VIH or 1.2 1.05 1.8 1.8 2.0 1.85 Output Voltage VIL 2.5 2.5 I0=-100 A 2.7 2.55 2.8 2.8 3.0 2.85 3.4 3.4 3.6 3.45 4.3 4.3 4.5 4.35 5.3 5.3 5.5 5.35 VI = VIH or VIL 3.0 2.48 2.40 2.20 I0=-6.0 mA VI = VIH or VIL 4.5 3.70 3.60 3.50 I0=-12 mA 0.2 0.2 0.15 VOL Low-Level VI = VIH or 1.2 0.2 0.2 0.15 2.0 Output Voltage VIL 0.2 0.2 0.15 2.7 I0=100 A 0.2 0.2 0.15 3.0 0.2 0.2 0.15 3.6 0.2 0.2 0.15 4.5 0.2 0.2 0.15 5.5 0.33 0.40 0.50 VI = VIH or 3.0 VIL I0=6.0 mA 0.40 0.55 0.65 VI = VIH or 4.5 VIL I0=12 mA VI=0 V IIL Low-Level 5.5 -0.1 -1.0 -1.0 Input Leakage Current Unit V V V V A DC ELECTRICAL CHARACTERISTICS (continuation) 3 IN74LVU04 Symbol IIH Parameter High-Level Input Leakage Current Quiescent Supply Current (per Package) Test VCC, Conditions V VI= V 5.5 Guaranteed Limit 25C -40C / 85C -40C / 125C min max min max min max 0.1 1.0 1.0 Unit ICC VI=0 or V IO = 0 A 5.5 - 4.0 - 20 - 40 A VI = V - 2.7 0.85 mA Additional 0.2 0.5 0.85 Quiescent 0.6V 3.6 0.2 0.5 Supply Current on input AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 k) Guaranteed Limit Test VCC 25C -40C / -40C / Unit Symbol Parameter Conditio V 85C 125C ns min max min max min max ns 100 80 70 VI=0 V or 1.2 tPHL Propagation 31 26 22 2.0 (tPLH) Delay, Input A V1 23 19 16 to Output Y tLH = tHL 2.7 18 15 13 (Figure 1 ) =2.5 ns 3.0 16 13 11 L = 50 4.5 pF RL = 1 k CI Input 5.5 7.0 pF Capacitance CPD Power Dissipation Capacitance (Per pF =25, VI=0V or VCC Inverter) 36 Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) - sum of the outputs ICC1 4 IN74LVU04 tHL 0.9 VX 0.1 0.9 VX 0.1 tLH V1 GND Input tPHL tPLH VOH Output Y VX=0.5 VCC VY VY VOL Figure 1. Switching Waveforms VCC VI PULSE GENERATOR DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators RT CL RL Figure 2. Test circuit 5 IN74LVU04 CHIP PAD DIAGRAM IZ74LVU04 1.33 0.03 13 12 11 10 09 1.42 0.03 14 08 07 01 02 03 04 05 06 Chip marking IN74LVU04 (x=0.130; y=0.130) Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC PAD LOCATION X 0.130 0.130 0.381 0.616 0.881 1.116 1.115 1.115 1.115 0.804 0.569 0.378 0.143 0.130 Y 0.463 0.230 0.126 0.126 0.126 0.126 0.631 0.846 1.181 1.194 1.194 1.194 1.194 0.813 6 |
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